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32-mbit (2 m 16/4 m 8) static ram cy62177esl mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-64709 rev. *c revised august 21, 2013 32-mbit (2 m 16/4 m 8) static ram features thin small outline package-i (tsop-i) configurable as 2 m 16 or as 4 m 8 static ram (sram) high-speed up to 55 ns wide voltage range: 2.2 v to 3.6 v and 4.5 v to 5.5 v ultra low standby power ? typical standby current: 3 a ? maximum standby current: 25 a ultra low active power ? typical active current: 4.5 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2, and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 48-ball tsop-i package functional description the cy62177esl is a high performance cmos static ram organized as 2 m words by 16 bits and 4 m words by 8 bits. this device features advanced circuit design to provide ultra low active current. it is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automat ic power-down feature that significantly reduces power co nsumption by 99 percent when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 20 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written to the location specified on the address pins (a 0 through a 20 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 0 a 1 a 9 a 10 power- down circuit bhe ble ce 2 ce 1 ce 2 ce 1 byte column decoder a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 20 2 m 16 ram array logic block diagram
cy62177esl mobl ? document number: 001-64709 rev. *c page 2 of 16 contents pin configuration ............................................................... 3 product portfolio ................................................................ 3 maximum ratings ............................................................... 4 operating range ................................................................. 4 electrical characteristics ....... ............................................ 4 capacitance ........................................................................ 5 thermal resistance ............................................................ 5 ac test loads and waveforms .. .............. .............. ........... 5 data retention characteristics ......................................... 6 data retention waveform .................................................. 6 switching characteristics .................................................. 7 switching waveforms ........................................................ 8 truth table ........................................................................ 11 ordering information ....................................................... 12 ordering code definitions ..... ...................................... 12 package diagrams ........................................................... 13 acronyms .......................................................................... 14 document conventions ................................................... 14 units of measure ......................................................... 14 document history page ................................................... 15 sales, solutions, and legal information ........................ 16 worldwide sales and design support ......... ........... ..... 16 products ...................................................................... 16 psoc? solutions ........................................................ 16 cypress developer community .................................. 16 technical support ................. .............. .............. .......... 16
cy62177esl mobl ? document number: 001-64709 rev. *c page 3 of 16 pin configuration figure 1. 48-pin tsop i pinout (front view) [1, 2] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we ce2 nc bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a21 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce1 a0 dnu product portfolio product v cc range (v) [3] speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max typ [4] max typ [4] max typ [4] max cy62177esl 2.2 v to 3.6 v and 4.5 v to 5.5 v 55 4.5 5.5 35 45 3 25 notes 1. nc pins are not connected on the die. 2. the byte pin in the 48-pin tsop-i package has to be tied to v cc to use the device as a 2 m 16 sram. the 48-pin tsop-i package can also be used as a 4 m 8 sram by tying the byte signal to v ss . in the 4 m 8 configuration, pin 45 is a21, while bhe , ble, and i/o 8 to i/o 14 pins are not used. 3. datasheet specifications are not guaranteed in the range of 3.6 v to 4.5 v. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c
cy62177esl mobl ? document number: 001-64709 rev. *c page 4 of 16 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential ....................................... ?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high z state [5, 6] ....................... ?0.3 v to v cc(max) + 0.3 v dc input voltage [5, 6] ................... ?0.3 v to v cc(max) + 0.3 v output current into outputs (low) ............................. 20 ma static discharge voltage (per mil-std-883, method 3015) ......................... ?? 2001 v latch-up current ????????????????????????????????????????????????????????????? 200 ma operating range device range ambient temperature v cc [7] cy62177esl industrial ?40 c to +85 c 2.2 v to 3.6 v and 4.5 v to 5.5 v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [8] max v oh output high voltage 2.2 v ?? v cc ? 2.7 v i oh = ?0.1 ma 2.0 ? ? v 2.7 v ? v cc ? 3.6 v i oh = ?1.0 ma 2.4 ? ? v 4.5 v ? v cc ? 5.5 v i oh = ?1.0 ma 2.4 ? ? v v ol output low voltage 2.2 v ? v cc ? 2.7 v i ol = 0.1 ma ? ? 0.4 v 2.7 v ? v cc ? 3.6 v i ol = 2.1 ma ? ? 0.4 v 4.5 v ? v cc ? 5.5 v i ol = 2.1 ma ? ? 0.4 v v ih input high voltage 2.2 v ? v cc ? 2.7 v 1.8 ? v cc + 0.3 v v 2.7 v ? v cc ? 3.6 v 2.2 ? v cc + 0.3 v v 4.5 v ? v cc ? 5.5 v 2.2 ? v cc + 0.3 v v v il input low voltage 2.2 v ? v cc ? 2.7 v ?0.3 ? 0.6 v 2.7 v ? v cc ? 3.6 v ?0.3 ? 0.7 [9] v 4.5 v ? v cc ? 5.5 v ?0.3 ? 0.7 [9] v i ix input leakage current gnd ? v i ? v cc ?1 ? +1 ? a i oz output leakage current gnd ? v o ? v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?3545ma f = 1 mhz ? 4.5 5.5 ma i sb2 [10] automatic power-down current ? cmos inputs ce 1 ? v cc ? 0.2 v or ce 2 ? 0.2 v or (bhe and ble ) ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v, f = 0, v cc = 3.6 v ?325 ? a notes 5. v il(min) = ?2.0 v for pulse durations less than 20 ns. 6. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 7. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 8. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c 9. under dc conditions the device meets a v il of 0.8 v. however, in dynamic conditions input low voltage applied to the device must not be higher than 0.7 v. 10. chip enables (ce1 and ce2), byte enables (bhe and ble ) and byte must be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating.
cy62177esl mobl ? document number: 001-64709 rev. *c page 5 of 16 capacitance parameter [11] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 15 pf c out output capacitance 15 pf thermal resistance parameter [11] description test conditions tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 44.66 ? c/w ? jc thermal resistance (junction to case) 12.12 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 table 1. ac test loads parameter 2.5 v 3.0 v 5.0 v unit r1 16667 1103 1800 ? r2 15385 1554 990 ? r th 8000 645 639 ? v th 1.20 1.75 1.77 v note 11. tested initially and after any design or proc ess changes that may effect these parameters.
cy62177esl mobl ? document number: 001-64709 rev. *c page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [12] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [13] data retention current v cc = 1.5 v, ce 1 ? v cc ? 0.2 v or ce 2 ? 0.2 v or (bhe and ble ) ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v ??17 ? a t cdr [14] chip deselect to data retention time ?0??ns t r [15] operation recovery time ? 55 ? ? ns data retention waveform figure 3. data retention waveform [16] t cdr v dr ? 1.5 v data retention mode t r ce 1 or v cc bhe . ble or v cc(min) v cc(min) ce 2 notes 12. typical values are included only for reference and are no t guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 13. chip enables (ce1 and ce2), byte enables (bhe and ble ) and byte must be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 14. tested initially and after any design or proce ss changes that may affect these parameters. 15. full device operation requires linear v cc ramp from v dr to v cc(min) ? 100 ? s or stable at v cc(min) ? 100 ? s. 16. bhe .ble is the and of both bhe and ble . chip is deselected by either disabling the chip enable signals or by disabling both bhe and ble .
cy62177esl mobl ? document number: 001-64709 rev. *c page 7 of 16 switching characteristics over the operating range parameter [17, 18] description 55 ns unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 6 ? ns t ace ce 1 low and ce 2 high to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [19] 5 ? ns t hzoe oe high to high z [19, 20] ? 18 ns t lzce ce 1 low and ce 2 high to low z [19] 10 ? ns t hzce ce 1 high and ce 2 low to high z [19, 20] ? 18 ns t pu ce 1 low and ce 2 high to power-up 0 ? ns t pd ce 1 high and ce 2 low to power-down ? 55 ns t dbe ble/bhe low to data valid ? 55 ns t lzbe ble /bhe low to low z [19] 10 ? ns t hzbe ble /bhe high to high z [19, 20] ? 18 ns write cycle [21] t wc write cycle time 55 ? ns t sce ce 1 low and ce 2 high to write end 40 ? ns t aw address setup to write end 40 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 40 ? ns t bw ble /bhe low to write end 40 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [19, 20] ? 20 ns t lzwe we high to low z [19] 10 ? ns notes 17. in an earlier revision of this device, under a specific applic ation condition, read and write operations were limited to swi tching of the byte enable and/or chip enable signals as described in the application note an66311 . however, the issue has been fixed and in production now, a nd hence, this application note is no longer applicable. it is available for download on our website as it contains information on the date c ode of the parts, beyond which the fix has been in production. 18. test conditions for all parameters other than tristate parame ters assume signal transition time of 1 v/ns, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in figure 2 on page 5. 19. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 20. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedence state. 21. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a writ e by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
cy62177esl mobl ? document number: 001-64709 rev. *c page 8 of 16 switching waveforms figure 4. read cycle 1 (address transition controlled) [22, 23] figure 5. read cycle 2 (oe controlled) [23, 24] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe high i cc i sb impedance oe ce 1 address v cc supply current bhe / ble data out ce 2 notes 22. the device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 23. we is high for read cycle. 24. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high.
cy62177esl mobl ? document number: 001-64709 rev. *c page 9 of 16 figure 6. write cycle 1 (we controlled) [25, 26, 27] figure 7. write cycle 2 (ce 1 or ce 2 controlled) [25, 26, 27] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 28 address we data i/o oe bhe / ble ce 1 ce 2 t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data note 28 t bw t sa address we data i/o oe bhe / ble ce 1 ce 2 notes 25. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inacti ve. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. data i/o is high impedance if oe = v ih . 27. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 28. during this period the i/os are in output state and input signals should not be applied.
cy62177esl mobl ? document number: 001-64709 rev. *c page 10 of 16 figure 8. write cycle 3 (we controlled, oe low) [29] figure 9. write cycle 4 (bhe /ble controlled, oe low) [29] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 30 address ce 1 ce 2 bhe / ble we data i/o t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 30 address ce 1 ce 2 bhe / ble we data i/o notes 29. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 30. during this period the i/os are in output state and input signals should not be applied.
cy62177esl mobl ? document number: 001-64709 rev. *c page 11 of 16 truth table ce 1 ce 2 we oe bhe ble inputs outputs mode power hx [31] xxx [31] x [31] high z deselect/power-down standby (i sb ) x [31] lxxx [31] x [31] high z deselect/power-down standby (i sb ) x [31] x [31] x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l high z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) read active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l high z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) write active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) note 31. the ?x? (don?t care) state for the chip enables and byte enables in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
cy62177esl mobl ? document number: 001-64709 rev. *c page 12 of 16 ordering information table 2 lists the cy62177esl mobl ? key package features and ordering codes. the table contains only the parts that are currently available. if you do not see what you are looking for, contact your local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions table 2. key features and ordering information speed (ns) ordering code package diagram package type operating range 55 CY62177ESL-55ZXI 51-85183 48-pin tsop-i (12 18.4 1 mm) pb-free industrial cy family: mobl sram 621 7 7 density: 32 mbit company id: cy = cypress e bus width: x16 process technology: 90 nm sl wide voltage range (3 v and 5 v) 55 speed grade zx package type: tsop i (pb-free) i temperature grades: i = industrial
cy62177esl mobl ? document number: 001-64709 rev. *c page 13 of 16 package diagrams figure 10. 48-pin tsop i (12 18.4 1 mm) z48a package outline, 51-85183 51-85183 *c
cy62177esl mobl ? document number: 001-64709 rev. *c page 14 of 16 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory tsop thin small outline package symbol unit of measure c degrees celsius mhz megahertz ? a microampere ma milliampere ns nanosecond ? ohm pf picofarad v volt w watt
cy62177esl mobl ? document number: 001-64709 rev. *c page 15 of 16 document history page document title: cy62177esl mobl ? 32-mbit (2 m 16/4 m 8) static ram document number: 001-64709 revision ecn orig. of change submission date description of change ** 3077028 rame 11/02/10 new data sheet *a 3103863 rame 12/07/2010 the specified part in the ordering information table is moved to production. no change in the datasheet. *b 3433813 tava 11/16/2011 removed footnote #1. pin #13 of figure 1 under pin configuration section changed from nc to dnu. *c 4101093 vini 08/21/2013 updated switching characteristics : added note 17 and referred the same note in ?parameter? column. updated in new template.
cy62177esl mobl ? document number: 001-64709 rev. *c revised august 21, 2013 page 16 of 16 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor corporation. all products and co mpany names mentioned in this document may be the trademarks of their respective holders. ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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